The present invention relates to a solid-state imaging device, and more particularly to an amplifying type solid-state imaging device or a solid-state imaging device such as a MOS (metal oxide semiconductor) solid-state imaging device.
As a demand that a solid-state imaging device becomes high in resolution is increased, an internal amplifying type solid-state imaging device has hitherto been developed, and other MOS type solid-state imaging devices also have been known so far.
As the internal amplifying type solid-state imaging device, there are mainly known a static induction transistor (SIT), an amplifying type MOS imager (AMI), a charge-modulation device (CMD), and various imaging device structures such as a BASIS (base-stored image sensor) using bipolar transistors as pixels.
The following amplifying type solid-state imaging device is known as one of such internal amplifying type solid-state imaging devices. This amplifying type solid-state imaging device accumulates photoelectrically-converted holes (signal charges) in a p-type potential well in an n-channel MOS transistor (pixel MOS transistor), and outputs the change of channel current based on a potential fluctuation (i.e., potential change in back gate) in the p-type potential well as a pixel signal.
On the other hand, the assignee of the present application has previously proposed a capacity loaded operation system amplifying type solid-state imaging device in which a sensitivity can be made uniform, a high resolution can be made, and a low power consumption can be realized.
FIG. 1 of the accompanying drawings shows an example of a capacity loaded operation system amplifying type solid-state imaging device. In this amplifying type solid-state imaging device 1, as shown in FIG. 1, light-receiving elements comprising a plurality of unit pixels (cells), e.g., pixel transistors, in this example, pixel MOS transistors 2 are arranged in a matrix fashion. Gates of pixel MOS transistors 2 on every rows are connected to vertical scanning lines 4 selected by a vertical scanning circuit 3 composed of a shift register 4, and drains thereof are connected to a power supply source VDD. Their sources at every columns are connected to vertical signal lines 5.
A load capacity element 8 for holding a signal voltage (electric charge) is connected through an operation MOS switch 7 to the vertical signal line 5. An operation pulse φOP is applied to the gate of the operation MOS switch 7. The load capacity element 8 is connected to the drain of a horizontal MOS switch 9, and the source of this horizontal MOS switch 9 is connected to a horizontal signal line 10.
In FIG. 1, reference numeral 11 denotes a horizontal scanning circuit comprising a shift register or the like. The horizontal scanning circuit 11 sequentially supplies horizontal scanning pulses φH [φH1, . . . φHi, φHi+1, . . . ] to the gates of the horizontal MOS switches 9 connected to the horizontal signal line 10.
A signal detecting means, in this example, a charge detecting circuit 16 comprising an operational amplifier 14 using an inverting amplifier, e.g., a differential amplifier, a detection capacity element 14 and a reset switch 15 is connected to the output terminal of the horizontal signal line 10.
Specifically, the horizontal signal line 10 is connected to an inverting input terminal of the operational amplifier 13 of the charge detecting circuit 16, and a predetermined bias voltage VB is applied to a non-inverting input terminal of the operational amplifier 13. This bias voltage VB is used to determine the potential of the horizontal signal line 10. The detection capacity element 14 is connected in parallel to the operational amplifier 13, i.e., the detection capacity element 14 is connected between the inverting input terminal of the operational amplifier 13 and an output terminal t1, and a reset switch for resetting the horizontal signal line 10 and the detection capacity element 14, e.g., MOS transistor 15 is connected in parallel to the detection capacity element 14.
In this amplifying type solid-state imaging device 1, during the horizontal blanking period where reading operation is carried out, vertical scanning signals (i.e., vertical selection pulses) φV [φV1, . . . φVn, φVn+1, . . . ] are sequentially applied to the scanning lines 4 of every row from the vertical scanning circuit 3 to sequentially select the pixel MOS transistors 7 of every column. Also, when the operation MOS switch 7 is turned on by the operation pulse φOP, the pixel MOS transistor 2 and the load capacity element 8 are turned on so that a signal charge is started being charged in the load capacity element 8 from the moment the operation MOS switch 7 is turned on. When the operation MOS switch 7 is turned off after the signal voltage is stabilized sufficiently, a signal voltage corresponding to a channel potential corresponding to the amount of signal charges (amount of holes) accumulated in the pixel MOS transistor 2 is held in the load capacity element 8.
The signal voltage held in the load capacity element 8 is flowed to the horizontal signal line 10 as electric charge when the horizontal MOS switches 9 are sequentially turned on by the horizontal scanning signals (i.e., horizontal scanning pulses) φH [φH1, . . . φHi, φHi+1, . . . ] supplied thereto from the horizontal scanning circuit 11 during the horizontal scanning period.
The signal charge flowed to the horizontal signal line 10 is demodulated to the detection capacity element 14 of the charge detecting circuit 16 using the operational amplifier 13 as a signal voltage, and is then outputted to the output terminal t1 as a video signal.
The detection capacity element 14 of the charge detecting circuit 16 turns on and resets the reset switch 15 by a reset pulse φR before the horizontal MOS switch 9 corresponding to the next pixel MOS transistor is turned on.
According to the amplifying type solid-state imaging device 1, when the signal voltage is held in the load capacity element 7, substantially no current is flowed to the vertical signal line 5 so that a uniform sensitivity can be obtained without being affected by a resistance of the vertical signal line 5 very much.
Further, since the load is the capacity element 7, signal charges cannot be fluctuated less unlike the load MOS transistor, and hence a vertical stripe-shaped fixed pattern noise (FPN) is difficult to be generated.
Further, since the channel potential of the pixel MOS transistor 2 becomes a potential held in the load capacity element 8 as it is, a sensitivity can be increased as compared with the case that the pixel MOS transistor is operated in the stationary state by the load MOS transistor, i.e., under the condition that a constant current is flowed to the channel.
Furthermore, a steady-state current is not flowed to the pixel MOS transistor 2, a power consumption can be decreased.
As the horizontal MOS switch 9 of this amplifying type solid-state imaging device 1, there is used a MOS transistor of which the structure is illustrated in FIG. 2.
In the MOS transistor 9, a source region 22S and a drain region 22D are formed on semiconductor regions separated by a field insulating layer (so-called LOCOS oxide layer) 21 provided by selective oxidation, and a gate electrode 23 made of polycrystalline silicon, for example, is formed between the source region 22S and the drain region 22D through a gate insulating film.
The gate electrode 23 is connected to the horizontal scanning circuit 11. A source electrode 24 and a drain electrode 24D are each made of Al, for example, and the drain electrode 24D is connected to the vertical signal line 5 through the operation MOS switch. The source electrode 24S is connected to the horizontal signal line 10. In FIG. 2, reference numeral 26 denotes a contact portion, and 27 an Al interconnection.
With the above-mentioned arrangement, since the source regions 22S of many horizontal switches 9 are connected to the horizontal signal line 10, a parasitic capacity of the horizontal signal line 10 is increased, thus lowering a detection sensitivity of the charge detecting circuit 16.